Current Openings
1. Physical Design Engineer
Primary Responsibilities and Requirements.
BE/B.Tech/ME/M.Tech 3 years to 15 years.
* He/She should be able to do top-level oor planning, PG Planning, Partitioning, Placement, Scan-Chain-Reordering,Clock Tree Synthesis,Timing Optimization, SI aware routing,Timing Analysis/closure and ECO tasks(timing and functional ECOs),SI closure, design rule checks(DRC),logical vs. Schematic(LVS) checks,Antenna checks. HE/She should have worked on 65nm or lower node designs with adv power techniques such as Voltage Islands, Power Gating and substrate-bias
* Provide technical guidance, mentoring to physical design engrs.
* Interface with front-end ASIC teams to resolve issues.
* Low Power Design-Voltage Islands, Power Gating, Substrate-bias techniques.
* Timing closure on DDR2/DDR3/PCIE interfaces.
* Excellent communication skills.
* Strong Background of ASIC Physical Design:Floor planning, P&R,extraction, IR Drop Analysis, Timing AND Signal Integrity closure.
* Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
* Expertise in scripting languages such as PERL, TCL.
* Strong Physical Verication skill set.
* Static Timing Analysis in Primetime or Primetime-SI.
* Good written and oral communication skills. Ability to clearly document plans.
* Ability to interface with different teams and prioritize work based on project needs
2. Analog Layout Engineer
Primary Responsibilities and Requirements.
BE/B.Tech/ME/M.Tech 3 years to 15 years.
* He/She should be able to act as focal point with customers, work and lead a team of 3-4 custom layout engineers on analog layout,
physical verication, maintaining PDKs, ealuating them. The candidates should have a strong expertise in some critical layouts such as PLL, DLL, LNA, VGA, ADC, LDO. He/She should be able to adapt to new technologies/tools/ows pretty quickly.
* Expertise in Custom Layout Standard Cells, I/O or special analog designs such as RF transceivers, LNA, VGA, PLL, DLL, LDO, Bandgap, VCO, ADC,DAC.
* Strong Layout Design Concepts.
* Experience in Pcell development, maintaining and modifying PDKs.
* Experience in Layout Design tools such as Virtuoso, Virtuoso-XL.
* Expertise in SKILL Programming Language.
* Experience in Physical verication.
* Exposure to Calibre, Hercules and Assura.
* Exposure to digital place & route.
* Should be able to mentor layout engineers and act as focal point with customers.
* Good understanding of Analog Design.
* Strong basics in process technology, fabrication techniques.
* Good written and oral communication skills. Ability to clearly document plans.
* Ability to interface with different teams and prioritize work based on project needs
3. Design Verification Engineer
Primary Responsibilities and Requirements.
BE/B.Tech/ME/M.Tech 3 years to 15 years.
* Develop verication testbench components for chip/module level using System Verilog, C/C++.
* Use Verication methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment.
* Dene and execute detailed verication plan from spec working with architects, designers, system engineers.
* Write tests, Debug tests, automate regression scripts and regression environment.
* Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verication completeness prior to tapeout.
* Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
* Excellent debugging skills in both SW and ASIC hardware.
* Must be good in building verication environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc.
* Prociency in scripting language like Perl, Tcl/Tk, Shell is a denite plus.
* Experience with simulators like nc Verilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy.
* Good understanding of latest formal verication techniques, assertions, properties is a plus.
* Understanding or prior experience with Industry standard protocols like USB, SPI, SATA, Ethernet, Display Port, SRIO etc is a denite plus.
* Understanding or Prior Experience in ARM/Tensillica Processor platforms is a denite plus.
* Good written and oral communication skills. Ability to clearly document plans.
* Ability to interface with different teams and prioritize work based on project needs.
4. Physical Verification Engineer
Primary Responsibilities and Requirements.
BE/B.Tech/ME/M.Tech 3 years to 15 years.
*Experience with different physical verication checks like DRC, LVS, Antenna, ERC, PERC, ESD etc.
* Experience in sign-off PDV tools like PDK Concepts, SVRF, Calibre.
* Experience in PnR tools like ICC/Innovus with regards to physical convergence.
* Layout design background and experience a plus.
* Strong scripting skills using Perl, TCL, other scripting languages to debug ow related issues and make enhancements as appropriate.
* Excellent verbal and written communication skills are required.
* Excellent interpersonal and analytical skills with the ability to work independently.
5. Logic Synthesis Engineer
Primary Responsibilities and Requirements.
BE/B.Tech/ME/M.Tech 3 years to 15 years.
* Timing (Constraints / Synthesis / STA) Timing ASIC Constraint development , Synthesis / STA.
* Strong experience in Logic/physical synthesis , STA , Lint and CDC checks , DFT , constraining , physical implementation Hands - on experience in timing analysis.
* Experience in doing SoC level timing analysis Should be familiar with timing analysis for hierarchical designs.
* Familiarity with different types interfaces like PCIe , NVMe / , USB, DDR etc.
* Should be procient with Synopsys' Prime Time for timing analysis.
* Good scripting skill in Tcl and Perl Familiarity with different physical design tools knowledge of Synopsys tools.
* Knowledge about data management is a denite plus.
* Good team player working with geo - dispersed cross cultural and cross functional teams.
* Good communication and interpersonal skills required.
